Currently, many image sensor pixel array designs employ a charge mode readout (“CMR”) architecture. Sample and reset values from individual pixels in a selected CMOS image sensor pixel array row are simultaneously read out through individual columns to a line memory, where they are stored on sample-and-hold capacitors until column readout. Upon column readout, stored sample and reset signals are routed to a switched capacitor amplifier and the resulting voltage signals output by this buffering amplifier are input to an analog-to-digital converter (“ADC”). An exemplary CMR readout design is presented in FIG. 1.
High-performance amplifiers are usually required in CMR's due to their poor feedback factor and high speed requirements, which increases the image sensor readout power usage drastically. In fact, the CMR amplifiers have become one of the most power-hungry components in today's CMOS image sensors.
One prior art solution which reduces the power consumption of the buffering amplifier is the use of a level-shifting circuit in the buffering stage, for example as described by S. Huang, et al., “Design of Analog Readout Circuitry with Front-End, Multiplexing for Column Parallel Image Sensors”, IEEE Int. Image Sensor Workshop, 7.08, June 2013. For example, a DAC-driven capacitive level shifting circuit may be used. An exemplary level-shifting CMR design is presented in FIG. 2. The level-shifting circuit imparts a fully differential output voltage swing to the amplifier, improving signal resolution, and also allowing the use of a lower power amplifier. However, this solution has various shortcomings:                1) the feedback factor is reduced by the feed forward capacitors present in the level shifting DAC, and higher power consumption is required;        2) the level-shifting circuit introduces more components and increases the area of the readout circuitry; and        3) the amplifier must be unity gain stable in the reset phase of the readout process;        
During the reset phase, the amplifier output is sampled onto the DAC capacitors in unity gain mode. The output needs to settle with adequate precision to attain the desired signal. This requirement creates a problem because using a typical two-stage op-amp with compensation capacitors, such capacitors must be sized such that the op-amp is stable for both the gain phase (which has a higher loop gain) and the reset phase (with unity gain). In order to reconcile these requirements, an op-amp with lower bandwidth is used in order to stay stable during the unity gain phase, requiring higher power consumption.
Accordingly, there is a need in the art for improvements to the prior art level-shifting CMR solution that overcome the shortcomings of such designs while maintaining the advantages thereof. Presented herein are novel circuits and associated methods which improve upon the level-shifting CMR readout designs of the prior art.